1. Field of the Invention
The present invention relates to a switching power supply device which includes a light load intermittent oscillation (burst mode) handling circuit.
2. Description of the Related Art
In a switching power supply device, since a switching loss becomes noticeable at the time of a light load, particularly, during standby mode, it is effective to decrease the number of switching operations per second to decrease the consumption of power. Therefore, a control system that is called an intermittent oscillation (burst mode) is preferably used as a means for decreasing the number of switching operations.
FIG. 13 illustrates the configuration of a switching power supply device adopting a burst mode control system, disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2008-245419. The switching power supply device is configured as a converter of a flyback system.
In FIG. 13, the output voltage of an alternating current power supply AP1 is full-wave rectified by a diode stack DS1, is smoothed by a capacitor C10, and becomes a direct current voltage Vi. The direct current voltage Vi is supplied to a primary winding N1 of an output transformer T10 through a power MOS transistor Q10 and a sense resistor R15 used for current detection. The power MOS transistor Q10 is turned on/off by a gate drive signal from a power supply control IC 100. This causes a pulse flow to be generated in the secondary winding N2 of the output transformer T10. The pulse flow is rectified by a diode D11, is smoothed by a capacitor C20, and is supplied to a load (not illustrated in the drawings).
A voltage that is output to the load is divided by resistors R11 and R12 and detected. The detected voltage (in the strict sense, a signal obtained by amplifying the difference between the detected voltage and a reference voltage) is input as a feedback signal to an FB terminal of the power supply control IC 100 through a photo coupler PC1.
Meanwhile, if a current flows through the secondary winding N2 of the output transformer T10, a voltage is also generated in an auxiliary winding N3. This voltage is rectified by a diode D12, is smoothed by a capacitor C30, and is supplied to a Vcc terminal serving as a power supply terminal of the power supply control IC 100.
The connection point of the diode D12 and the capacitor C30 is connected to a ZCD terminal of the power supply control IC 100 through a resistor R13. The connection point of the power MOS transistor Q10 and the sense resistor R15 for current detection is connected to an IS terminal (a terminal used to input a detection value of the current flowing through the power MOS transistor Q10) of the power supply control IC 100.
The power supply control IC 100 includes a GND terminal, an OUT terminal which outputs a gate drive signal (a switching pulse) of the power MOS transistor Q10, and a VH terminal which supplies a current from a high voltage system to the Vcc terminal. C40 and C50 indicate capacitors, ZD1 indicates a shunt regulator, and R14 indicates a resistor for current restriction.
The power supply control IC 100 outputs a gate drive signal according to a load state, on the basis of the feedback signal input to the FB terminal to control switching of the power MOS transistor Q10 with the gate drive signal. FIG. 14 is a circuit diagram illustrating the configuration of the power supply control IC 100.
In FIG. 14, a burst circuit 101 includes a comparator OP1, pull-up resistors R101 and R102, and a switch element SW1. In the comparator OP1, a positive input terminal is connected to the FB terminal and a negative input terminal is connected to a reference voltage source that generates a burst threshold voltage Vth. The pull-up resistor R101 is connected between a Vreg power supply terminal, to which an output voltage Vreg of a regulator (not illustrated in the drawings) is applied, and the FB terminal. The pull-up resistor R102 is connected between the Vreg power supply terminal and the FB terminal through a switch element SW10.
With this configuration, the comparator OP1 compares a partial voltage (that is, voltage Vfb) obtained by dividing the voltage Vreg by pull-up resistances (R101 and R102) and by on resistance of a photo transistor (see FIG. 13) of the photo coupler PC1 externally attached to the FB terminal, with the burst threshold voltage Vth. The voltage Vfb of the FB terminal becomes lower than the voltage Vreg by the amount of voltage dropped due to the pull-up current (and the pull-up resistances).
An output of the comparator OP1 is input to the output control circuit 102 which controls switching of the switching power supply and is also input to the switch element SW10 as a control signal.
The voltage Vfb of the FB terminal is also input to the output control circuit 102. In addition, a signal from the IS terminal, a signal from the ZCD terminal, and an output signal of an under voltage lockout (UVLO) circuit 103 are input to the output control circuit 102. The output control circuit 102 generates a signal which controls turning on/off the power of the MOS transistor Q10 which is a switching element, from these signals. The signal is output from the OUT terminal through a driver 104.
More specifically, the output control circuit 102 detects the valley portion of the signal that is input to the ZCD terminal and determines the start of an on-period of the power MOS transistor Q10. In a normal operation, if the signal from the IS terminal becomes equal to the voltage Vfb (or divided voltage thereof) of the FB terminal or equal to an internal reference voltage, the power MOS transistor Q10 is turned off and the on-period ends. When a signal of a low (L) level is input from the burst circuit 101 or a signal, which represents detection of an abnormally low voltage, is input from the UVLO circuit 103, the output control circuit 102 stops the output of the signal which turns on/off the power MOS transistor Q10.
The input terminal of a start circuit 105 is connected to a VH terminal and the output terminal thereof is connected to the Vcc terminal. An input of the start circuit 105 and/or an input to the Vcc terminal become/becomes an internal power supply of the power supply control IC 100. The UVLO circuit 103 receives the power supply voltage Vcc from the Vcc terminal, compares the received voltage with the reference voltage, and performs control of stopping an on/off operation of the power MOS transistor Q10 in an abnormally low voltage state.
The switching power supply device illustrated in FIG. 13 performs the operation of a light load→an increase in an output voltage (since a load current flowing from the capacitor C20 decreases, a current supplied from the secondary winding N2 of the output transformer T10 increases, which increases an output voltage which is a voltage between both ends of the capacitor C20)→an increase in a light emitting amount of an LED of the photo coupler PC1→a decrease in the on resistance of the photo transistor of the photo coupler PC1→a decrease in the voltage Vfb of the FB terminal. This is because an element (photo transistor) where the resistance value decreases when a load becomes light is connected to the FB terminal and the FB terminal is connected to the Vreg terminal through the pull-up resistors R101 and R102 illustrated in FIG. 14. One pull-up resistor R102 is disconnected by the switch element SW10. This causes the burst circuit 101 to enter a state of hysteresis.
In a normal operation mode other than an ultra-light load state, the voltage Vfb of the FB terminal is Vfb>Vth. In this case, since the output level bur of the comparator OP1 becomes a high (H) level, the power supply control IC 100 performs a switching operation and the switch element SW10 is turned on. Therefore, if resistance values of the pull-up resistors R101 and R102 are set to r1 and r2, the pull-up current Ifb1 in the normal operation mode is represented by the following Equation.Ifb1=(Vreg−Vfb)/(r1·r2/(r1+r2))  (1)
In the light load mode that is the ultra-light load state, the voltage Vfb of the FB terminal is in the state of Vfb<Vth. In this case, since the output level of the comparator OP1 becomes the L level, the power supply control IC 100 stops the switching operation and the switch element SW10 is turned off. Therefore, the pull-up current Ifb0 in the light load mode is represented by the following Equation.Ifb0=(Vreg−Vfb)/r1  (2)
As such, the pull-up current of the FB terminal is switched according to a detection level of the light load. In addition, overshoot or undershoot is generated in the voltage Vfb of the FB terminal due to switching. In the switching power supply device having the above configuration, an intermittent operation frequency having a long cycle is obtained which gives continuous pulses during an overshoot period and stops the switching operation during an undershoot period.
In the undershoot period, since the switching is stopped and hence power is not supplied from the primary side to the secondary side, the voltage Vfb increases halfway and the switching operation restarts when the voltage Vfb becomes more than the voltage Vth. If the overshoot period arrives and the switching operation restarts, power that is more than the power consumed by the load is supplied from the primary side to the secondary side. Therefore, the voltage Vfb decreases halfway and the switching operation is stopped when the voltage Vfb becomes more than the voltage Vth. This is a summary of the burst mode.
That is, when the load becomes lighter than about 10% of the rated load, the switch element SW10 is turned on/off and the voltage Vfb (feedback voltage) of the FB terminal oscillates in the form illustrated in an upper portion of FIG. 15. In this case, as illustrated in the lower portion of FIG. 15, continuous pulses that are generated in a short on-period (overshoot period) are output intermittently from the OUT terminal, with a cycle of the sum of the on-period and a long off-period (undershoot period). At the time of a heavy load, the pulses are continuously output.
A switching power supply device which performs a switching operation intermittently when the load becomes lighter is suggested by Japanese Patent Application Laid-Open (JP-A) No. 2006-149104. Since the switching power supply device that is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2006-149104 decreases the noise of a transformer when the mode is switched to low frequency mode or standby mode, the switching power supply device is configured to change a reference voltage which is used to determine switching to the low frequency mode or to the standby mode by the input voltage.
Meanwhile, in the switching power supply device that is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2008-245419, when the burst threshold voltage Vth increases, the burst power increases and hence the consumption of power decreases. Conversely, when the burst threshold voltage Vth decreases, the burst power decreases and hence the consumption of power increases.
Herein, the burst power will be described. The burst power refers to power that is output to the load at the moment in which the burst mode arrives and the switching operation of the switching element is stopped. A high burst threshold voltage Vth means that the voltage Vfb of the FB terminal is high when the mode has become the burst mode. The voltage Vfb of the FB terminal serves as a reference to determine the off timing of the power MOS transistor Q10 and is compared with a detection signal (voltage of Rs) of the current flowing through the power MOS transistor Q10. Therefore, when the burst threshold voltage Vth is high, that is, the voltage Vfb of the FB terminal is high, the power MOS transistor Q10 is not turned off until a large current flows through the power MOS transistor Q10. For this reason, the burst power increases.
Meanwhile, in the switching power supply device, if a switching rate of the pull-up resistors R101 and R102 becomes high, the burst frequency becomes low and the output ripple becomes high. In contrast, if the switching rate of the pull-up resistors becomes low, the burst frequency becomes high and the output ripple becomes low.
If A=R101 and B=R101·R102/(R101+R102) are set, the switching rate (change rate) of the pull-up resistors is defined as follows.Switching rate=(A−B)/B=R101/R102  (3)
The burst frequency is a vibration frequency of the voltage Vfb of the FB terminal in the burst mode. Therefore, the burst frequency does not mean a switching frequency during the burst mode.
In the switching power supply device, when the switching power supply device operates in the burst mode, because the burst frequency is generally in a range of 200 Hz to 2 kHz which is a frequency range in the audible zone, an abnormal noise by a magnetostrictive sound from the transformer T10 will cause a problem.
The burst power and the burst frequency determine whether it is easy to hear an abnormal noise. That is, it is easy to hear the abnormal noise when the burst power is large at the same burst frequency and it is easy to hear the abnormal noise when the burst frequency is high in the same burst power.
Meanwhile, a charging current of the transformer T10 that is detected by the resistor Rs increases when the voltage input to the transformer T10 increases, with respect to the same feedback voltage Vfb, because of the delay (about 200 ns) by a drive path and the delay (about 100 ns to 500 ns) by a current detection path. Thereby, the output power increases. Therefore, when the input voltage increases, the burst power increases.
Since gain of a power control loop increases when the input voltage increases, the burst frequency becomes high and the output ripple decreases.
The following Table 1 illustrates collection of the above operations.
TABLE 1Input voltage (Vi)highlowOutput ripplelowhighBurst power →large → largesmall → smallabnormal noiseBurst frequencyhigh (easy to hear)lowBurst threshold voltagehighlowConsumption powerlowhighBurst power → abnormallarge → largesmall → smallnoiseSwitching rate (changehighlowrate) of pull-up resistorsOutput ripplehighlowBurst frequencylowhigh (easy to hear)
Therefore, if the input voltage is set to Vi, the burst power is set to Pburst, the burst frequency is set to Fburst, the output ripple is set to Vo-rip, standby power is set to Psdy, and an abnormal noise level is set to Paud, a mutual relation thereof is represented as illustrated in FIG. 16.
That is, when the input voltage is high, because the burst power Pburst is large and the burst frequency Fburst is high, the abnormal noise level Paud becomes high. Meanwhile, when the input voltage is low, because the burst power Pburst is small, the consumption power (for example, standby power Psdy) increases and the output ripple Vo_rip also increases.
For this reason, in the switching power supply device, it is difficult to realize low consumption of power, a low abnormal noise, and a low output ripple over an entire input voltage range at the time of the burst operation.
In addition, in the switching power supply device that is described in JP-A No. 2006-149104, it is difficult to realize low consumption of power, a low abnormal noise, and a low output ripple over an entire input voltage range, due to the structure thereof.